[理工] [OS & 計組]-清大98- 資工所

看板Grad-ProbAsk作者 (Cerscent)時間16年前 (2010/01/10 12:05), 編輯推噓1(105)
留言6則, 3人參與, 最新討論串1/1
5.What are the drawbacks of client-server architecture? 請問一下client-server architecture是什麼東西? 查課本也找不太到 9.consider a 5-stage pipelined datapath where ALU computation is performed at the third stage and data memory read is performed at the fourth stage. We have a program of 1000 instruction is the format of "load,add,load,add,..". Each add instruction is form "add $a,$b,$c"which performs $a = $b + $c. Each load instruction is form "load $t,k($s)"which performs $t = memory[$s+k] Suppose each add instruction depends(and only depends on)the load instruction right before it.Each load instruction also depends(and only depends ) on the add instruction right before it. With forwarding,what would be actual CPI? 這題他沒說add和load須要幾個cycle 所以我就當一個stage一個cycle 並且add在load的左側load不須stall cycle 但load在add左測加上forwarding技術add需 sall 1 cycle 因此add要6個cycle load要5個 所以CPI = 500*(5+6)/1000 = 5.5 不知道這樣算對嗎? 10. Explain the ideas behind the following instruction-set-architecture design chaos? (a)Keep all instruction a single size. (b)Have 32 reigisters rather than many more. a.我想是 simplicity favors regularity b. smaller is faster 不知道這樣對嗎 請會的版友幫我解一下疑惑 先在這說聲謝謝了 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 114.43.160.197

01/10 13:28, , 1F
1.PTT應該就是一個例子. 2.要考慮它是pipeline, 指令
01/10 13:28, 1F

01/10 13:29, , 2F
可以重疊, 約3個cycle完成2個指令,CPI=1.5.
01/10 13:29, 2F

01/10 13:30, , 3F
3. 我的想法跟你是一樣的. 有錯請更正~
01/10 13:30, 3F

01/10 14:19, , 4F
對後,pipeline不考慮stall的話是1個cycle完成一道嘛
01/10 14:19, 4F

01/10 14:20, , 5F
我都忘了,謝謝<(_ _)>
01/10 14:20, 5F
※ 編輯: aideliemoon 來自: 114.43.160.197 (01/10 14:26)

01/10 22:32, , 6F
3.正確
01/10 22:32, 6F
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