[理工] [計組]-cache 計算

看板Grad-ProbAsk作者polomoss (小澤)時間14年前 (2010/01/07 15:43)推噓3(3推 0噓 3→)

留言6則, 4人參與討論串1/1

The processor has a 32KB 1-level cache and a 256KB 2-level cache on chip 1-level cache is 4-way associative and 2-level is fully associative. Assume the word size is 32bits and the block size for both caches is 32 bytes. 求 tag index Block offset 1-level 2-level 謝謝~可以列式算嗎? -- ┌這篇文章讓您覺得？─────────────────────────────┐ │ │ │ 一"一 \ / >\\\< ╯ ╰ ∩ ∩ ▁ ▁ ＞＿＜ㄧㄧ+ │ │ 皿 ε □ ▽ ▇Δ ▇ ╰╯ ╯ │ │ 北七亂喔害羞莎笅爽啦哭爸ＸＤ科科 │ └──────────────────────────────────────┘ -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 122.116.14.2

推

assassin88

01/07 22:59, , 1^F

01/07 22:59, 1^F

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polomoss

01/07 23:18, , 2^F

01/07 23:18, 2^F

推

james1815

01/07 23:51, , 3^F

01/07 23:51, 3^F