[問題] 計組－管線指令

看板Grad-ProbAsk作者bernachom (Terry)時間17年前 (2009/05/09 00:54)推噓1(1推 0噓 9→)

留言10則, 4人參與討論串1/1

請教一下 Schedule the following instruction segment into a superscaler pipeline for MIPS. Assume that the pipeline can execute one ALU Or branch instruction and one data transfer instruction concurrently. For the best, the instruction segment can be executed in four clock cycles. Fill in the instruction identifiers into the table. NOte that data dependency should be taken into account. (Identifier) (Instruction) In-1 loop: lw $t0.0($1) In-2 addu $t0.$t0.$s2 In-3 sw $t0.0($1) In-4 addi $s1.$s1,-4 In-5 bne $s1.$zero.Loop ＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿ ▕clock ▕ alu or branch instruction ▕data transfer instruction ▕ ▕＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿ ▕1＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕ ▕2＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕ ▕3＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕ ▕4＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕＿＿＿＿＿＿＿＿＿＿＿＿＿＿▕ 表格我盡力了...不會畫... 麻煩了，謝謝 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 61.228.97.36 ※ 編輯: bernachom 來自: 61.228.97.36 (05/09 00:55)

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