[理工] 邏輯設計的問題

看板Grad-ProbAsk作者 (...)時間17年前 (2009/03/27 15:43), 編輯推噓0(000)
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Design a timing circuit which provides an output signal that stays on for exactly eight clock cycles.A start signal sends the output to the 1 state, and after eight clock cycles the signal returns to the 0 state. 有人知道這題的邏輯電路怎麼畫嗎?? 感謝.. -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 118.166.170.43
文章代碼(AID): #19p8E8RQ (Grad-ProbAsk)