[問題] 97中正電機計組
2.Consider a program with the fpllowing instruction mix:
instruction type frequency
Load 25%
Store 15%
Branch 20%
ALU 40%
suppose any miss will cause a stall, please compute the CPI of this program
running on a pipelined machine with no instruction cache misses, no hazards,
a 98% data cache hit rate, and a miss penalty of 50 clock cycles.
no instruction cache misses,no hazards
這樣CPI是多少?1嗎?
data cache miss rate=2%
CPI=1+0.02*(0.25+0.15)*50=1.4
有錯請指正
4.Suppose a machine uses 32-bit physical address
If we consider a 2 way set-associative cache with 10 bit cache index and
32-byte cache blocks.
please calculate:
(a)The number of blocks in the cache.
(b)The size of the block offset.
(c)The size of the tag.
我的答案是
tag=17 bit index=10 bit block offset=5 bit
(a)2048
(b)2048* 5 bit=10240 bit
(c)2048*17 bit=34816 bit
有錯請指正
謝謝
另外 有第五題的答案嗎?
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※ 編輯: darvishyu56 來自: 218.175.169.105 (03/24 12:08)
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