[問題] 中山數位電路(庚組)
97年的中山數位電路
Problem3
Design a circuit that implements the negative-edge-triggered D flip-flop
with Clear and Preset using the basic gates such as NOT,AND,OR,
NAND, and NOR.
Problem5
Design a four-bit carry-lookahead adder using the basic gates such as NOT,
AND,OR,NAND,NOR and XOR.(10%) By the four-bit carry-lookahead adder module
(named CLA4), design a 16-bit carry-lookahead adder(5%).Let the basic gates
take the same delay time as 1d. Determine the delay time of the critical path
of the 16-bit carry-lookahead adder(5%).
Problem6
(a)Write the code for a negative-edge-triggered D filp-fiop with synchronous
reset in VHDL or Verilog HDL.
(b)In VHDL or Verilog HDL, write the code for the traffic light controller,
whose lighting sequences are as Figure P6. After the red lamp lights 3 cycles,
the green lamp light 2 cycles. After the green lamp lights,the yellow lamp
lights1 cycle.
拜託各位大大
因為小弟實在不太會這數位電路
所以煩請各位大大 賜給小弟解答
感激萬分
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