[問題] SystemVerilog的interface/port
(已解決, 自己搞錯方向 sorry)
小弟根據參考書籍寫一個測試,
在連接Testbench跟Arbiter之間用Interface時, 沒問題
但改用port的時候會出現error
有點不解原因, 希望好心人幫我解惑Q_Q
// Environment:
// EDA playground
// Tool & Sim. = Synopsys VCS 2019.06
`include "arb_if.sv"
`include "myArb.sv"
`include "myTest.sv"
module top;
bit clk;
always #50 clk = ~clk;
arb_if arbif (clk);
/* this one is executable
arb_with_ifc a1 (arbif);
*/
/* this one will fail with error: */
/* The port 'arbif' of module 'arb_with_ifc' whose type is interface
'arb_if' is left unconnected.
It is illegal to leave the interface ports unconnected.
The interface instance is 'a1' in file testbench.sv at line 16.
Please make sure that all the interface ports are connected.
*/
arb_with_ifc a1 (.grant (arbif.grant),
.request (arbif.request),
.rst (arbif.rst),
.clk (arbif.clk));
test_with_ifc t1 (arbif);
endmodule : top
Appendix -------------- arb_if.sv
interface arb_if(input bit clk);
logic [1:0] grant, request;
bit rst;
endinterface
Appendix -------------- myArb.sv
module arb_with_ifc (arb_if arbif);
always @(posedge arbif.clk or posedge arbif.rst)
begin
$display("ARB %0t: req = %p, gnt = %p, rst = %p", $time, arbif.request,
arbif.grant, arbif.rst);
if (arbif.rst) begin
arbif.grant <= '0;
$display("ARB %0t: req = %p, gnt = %p, rst = %p(1'b1)", $time, arbif.
request, arbif.grant, arbif.rst);
end
else if (arbif.request[0]) begin
arbif.grant <= 2'b01;
$display("ARB %0t: req = %p(2'bx1), gnt = %p, rst = %p", $time, arbif.
request, arbif.grant, arbif.rst);
end
else if (arbif.request[1]) begin
arbif.grant <= 2'b10;
$display("ARB %0t: req = %p(2'b1x), gnt = %p, rst = %p", $time, arbif.
request, arbif.grant, arbif.rst);
end
else begin
arbif.grant <= '0;
$display("ARB %0t: req = %p(else), gnt = %p, rst = %p", $time, arbif.
request, arbif.grant, arbif.rst);
end
end
endmodule
Appendix -------------- myTest.sv
module test_with_ifc (arb_if arbif);
initial begin
@(posedge arbif.clk);
arbif.request <= 2'b01;
$display("TEST %0t: Drove req = %p(01), gnt = %p, rst = %p", $time, arbif.
request, arbif.grant, arbif.rst);
repeat (2) begin @(posedge arbif.clk);
$display("TEST (%0t) test", $time);
end
$display("TEST %0t: req = %p, gnt = %p, rst = %p", $time, arbif.request,
arbif.grant, arbif.rst);
if (arbif.grant != 2'b01)
$display("TEST %0t: Error! reg = %p, gnt = %p != 2'b01, rst = %p", $time,
arbif.request, arbif.grant, arbif.rst);
else
$display("TEST %0t: Success! reg = %p, gnt = %p == 2'b01, rst = %p", $
time, arbif.request, arbif.grant, arbif.rst);
$finish;
end
endmodule
--
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自問自答:
top的a1從interface改用port,
是為了arb_with_ifc是用port的寫法的case
Appendix -------------- myArb.sv
module arb_with_ifc (output logic [1:0] grant,
input logic [1:0] request,
input bit rst, clk);
always @(posedge clk or posedge rst)
begin
$display("ARB %0t: req = %p, gnt = %p, rst = %p", $time, request, grant,
rst);
if (rst) begin
grant <= '0;
$display("ARB %0t: req = %p, gnt = %p, rst = %p(1'b1)", $time, request,
grant, rst);
end
else if (request[0]) begin
grant <= 2'b01;
$display("ARB %0t: req = %p(2'bx1), gnt = %p, rst = %p", $time, request
, grant, rst);
end
else if (request[1]) begin
grant <= 2'b10;
$display("ARB %0t: req = %p(2'b1x), gnt = %p, rst = %p", $time, request
, grant, rst);
end
else begin
grant <= '0;
$display("ARB %0t: req = %p(else), gnt = %p, rst = %p", $time, request,
grant, rst);
end
end
endmodule
※ 編輯: homer00 (123.110.78.153 臺灣), 11/10/2019 13:23:07
→
11/10 19:26,
4年前
, 1F
11/10 19:26, 1F
→
11/10 19:26,
4年前
, 2F
11/10 19:26, 2F