[問題] Verilog syntax error
小弟目前 verilog 語法問題 題目如下
Create 16 D flip-flops. It's sometimes useful to only modify parts of a group
of flip-flops. The byte-enable inputs control whether each byte of the 16
registers should be written to on that cycle. byteena[1] controls the upper
byte d[15:8], while byteena[0] controls the lower byte d[7:0].
resetn is a synchronous, active-low reset.
All DFFs should be triggered by the positive edge of clk.
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always@(posedge clk) begin
if (~resetn) begin
q=8'b00000000;
end
else begin
case (byteena)
2'b1X: assign q[15:8] = d[15:8];
2'bX1: assign q[7:0] = d[7:0];
endcase
end
end
endmodule
問題在case 的部分 compile error
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※ 編輯: gecer (122.121.17.136 臺灣), 11/02/2019 09:21:37
推
11/02 09:21,
6年前
, 1F
11/02 09:21, 1F
→
11/02 09:42,
6年前
, 2F
11/02 09:42, 2F
→
11/02 09:47,
6年前
, 3F
11/02 09:47, 3F
推
11/02 09:54,
6年前
, 4F
11/02 09:54, 4F
→
11/02 09:55,
6年前
, 5F
11/02 09:55, 5F
推
11/02 12:09,
6年前
, 6F
11/02 12:09, 6F
推
11/03 14:31,
6年前
, 7F
11/03 14:31, 7F