[問題]請教有關這個 Verilog 除頻器的問題
小弟最近需要做一個FPGA的i2c master
不過因為之前沒有接觸過
所以看了幾本書之後，又照著網路的幾個範例兜出架構
但是跑 semilution時一直沒辦法讓除頻過的SCL送出波型
Trigger的條件明明都有達成，該拉的狀態也都確認過了
卡了兩天左右實在抓不到方向
硬著頭皮上來問各位大神，希望能幫忙解惑哪個地方有問題
================Verilog Module
`timescale 1ns / 1ns
module SRAM_I2C(
clk_10us,reset,SDA,SCL,
bit_state,
write_down,
read_data,read_down,
Mux_EN1,Mux_EN2,Mux_EN3,Mux_EN4);
input clk_10us,reset;
inout SDA;
output reg SCL;
output reg Mux_EN1,Mux_EN2,Mux_EN3,Mux_EN4;
output reg [7:0]bit_state;
output reg write_down,read_down;
output reg [7:0]read_data;
reg isOut,tx_SDA;
reg [1:0]cnt;
reg [4:0]byte_state;
reg [7:0]write_data;
//for address use
parameter
write_address =8'b0000_0000,
write_chipaddress =8'b0000_0000,
write_bit =8'b0000_0000;
assign SDA = isOut ? tx_SDA : 1'bz;
//CLK Div for 10us
always @(posedge clk_10us or negedge reset)
begin
if(!reset)
cnt <=0;
else begin
if(cnt ==3)
cnt <=0;
else
cnt <= cnt +1'b1;
end
end
always @(posedge clk_10us or negedge reset)
begin
if(!reset)begin
tx_SDA <=0;
SCL <=0;
isOut <=0;
bit_state <=0;
byte_state <=0; //Check bytes
write_data <=0;
write_down <=1;
read_down <=0;
read_data <=0;
buf_time<=0;
Mux_EN1<=0;
Mux_EN2<=0;
Mux_EN3<=0;
Mux_EN4<=0;
end
else if(write_down==1 && read_down==0)begin//read enable
case(bit_state)
0:begin//start
if(cnt==0)begin SCL<=1;tx_SDA<=1;isOut <=1;end
if(cnt==1)begin SCL<=1;tx_SDA<=1;end
if(cnt==2)begin SCL<=1;tx_SDA<=0;end
if(cnt==3)begin SCL<=0;tx_SDA<=0;bit_state<=bit_state +1;
if(byte_state==3)write_data<=8'b10100001;else
write_data<=write_address;end
end
default:begin isOut <=0;end
endcase
end
end
endmodule
================Test Bench
`timescale 100ns / 100ns
module SRAM_I2C_TB;
// Inputs
reg clk_10us;
reg reset;
// Outputs
wire SCL;
wire [7:0] bit_state;
wire [7:0] read_data;
wire Mux_EN1;
wire Mux_EN2;
wire Mux_EN3;
wire Mux_EN4;
wire SDA;
SRAM_I2C uut (
.clk_10us(clk_10us),
.reset(reset),
.SDA(SDA),
.SCL(SCL),
.bit_state(bit_state),
.write_down(write_down),
.read_data(read_data),
.read_down(read_down),
.Mux_EN1(Mux_EN1),
.Mux_EN2(Mux_EN2),
.Mux_EN3(Mux_EN3),
.Mux_EN4(Mux_EN4)
);
//Generate CLK
reg [7:0] bit_states;
always begin
#50 clk_10us=!clk_10us;
end
initial begin
// Initialize Inputs
#0;
clk_10us = 0;
reset = 1;
#30;
reset = 0;
#5000 $finish;
end
endmodule
--
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※ 編輯: ghost008 (123.110.178.209), 08/30/2018 23:24:02
→
08/31 12:26,
5年前
, 1F
08/31 12:26, 1F
歹勢 我知道可能效率很差或是寫得很外行
不過我希望第一步的Waveform要能正確輸出，再慢慢修改
※ 編輯: ghost008 (118.166.219.36), 08/31/2018 12:33:20
→
08/31 12:42,
5年前
, 2F
08/31 12:42, 2F
→
08/31 12:43,
5年前
, 3F
08/31 12:43, 3F
原來是initial的SCL=0 是Activie low，這樣轉態會讀不到
現在可以動了 非常感謝!!!
※ 編輯: ghost008 (118.166.219.36), 08/31/2018 13:17:24