[問題] 請教verilog pulse產生個數問題
找不到專門的版所以發在這裡詢問高手
以下是我的code:
module rising_pwm_10bit(clk,rst_n,iduty,opwm);
input clk,rst_n;
input [9:0]iduty;
output reg opwm;
reg [9:0]count;
reg [9:0]duty;
always@(negedge rst_n or posedge clk)
begin
if (!rst_n)
count = 0;
else
begin
count = count + 1;
if (count == 0)
duty = iduty;
end
end
always@(posedge clk)
begin
if(duty==0)
opwm = 0;
else if(duty >= count)
opwm = 1 ;
else
opwm = 0;
end
endmodule
想請問一下如果想要只產生指定個數個pulse(例如:100個)要如何做呢
新手多多包含謝謝~
--
※ 發信站: 批踢踢實業坊(ptt.cc), 來自: 223.137.139.126
※ 文章網址: https://www.ptt.cc/bbs/Electronics/M.1484117993.A.54F.html
推
01/11 15:40, , 1F
01/11 15:40, 1F
→
01/11 18:04, , 2F
01/11 18:04, 2F