[問題] design compiler遇到的timing問題
我的design裡面有用到Artison memory compiler產生出來的register file
但在合成完report timing時發現了問題
timing report如下
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.10 0.10
Q_SignMem1/Ent[2].BlkSgnQ[1].SgnMem2/CLK (RF_SP_42_128)
0.00 0.10 r
Q_SignMem1/Ent[2].BlkSgnQ[1].SgnMem2/Q[109] (RF_SP_42_128)
999.00 999.10 r
Q_SignMem1/qSgnQ[2][2][237] (Q_SignMem) 0.00 999.10 r
U26919/Y (OAI222X4) 0.11 999.21 f
U56048/Y (AOI211X1) 0.10 999.31 r
genN[2].genZ[237].Recover1/sgnQ (Recover_182) 0.00 999.31 r
genN[2].genZ[237].Recover1/U1/Y (XOR2X1) 0.11 999.42 f
genN[2].genZ[237].Recover1/sgnR (Recover_182) 0.00 999.42 f
.
.
.
它的clk to Q的delay顯示出來是999
所以可想而知最後算出來的slack也是一個負很大的數
但實際情況應該不是這樣吧?
請問這邊要下什麼指令來修正? 謝謝
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