[問題] verilog同樣的電路，確有不同的結果?
小弟不才有一個小小疑問請想請教各位先進。
小弟作了一個小實驗，HDL大概長這樣:
output reg IQCLK;
always@(posedge EXTERNAL_CLK) begin
if(DATA_READ_CLK) begin
IQCLK <= 1;
end
else begin
IQCLK <= 0;
end
end
output reg IQWRT;
always@(posedge EXTERNAL_CLK) begin
if(DATA_READ_CLK) begin
IQWRT <= 1;
end
else begin
IQWRT <= 0;
end
end
===========================================
小弟的問題是，在作timing simulator的時候發現IQWRT上拉電位的時間點都比
IQCLK的速度還要在快一點??Why?????
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※ 編輯: gn00446610 (140.124.181.210), 07/05/2014 14:50:02
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