[問題] MOS 漏電流觀念問題
過去電子學沒有學得很好
想請問懂電子學的人可以指證我這想法是否有誤
以MOS為例,
1.當漏電流(subthreshold current)產生時,是因為MOS不導通,
D端和S端的電壓差造成漏電流。
2.當漏電流(gate-oxide current)產生時,是因為氧化層太薄,當MOS導通時
會產生閘極漏電流(Igd,Igs,Igb)
總結:MOS導通=>Igate,MOS不導通=>Isub
以上的觀念是否有誤呢??
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◆ From: 1.172.188.42
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先感謝上面兩位的告知,目前因為要將電路加上Body-bias機制
想先釐清就以總結的那樣想法去做Body-bias會不會有問題?
而我的想法是說 Pull-down 的NMOS(Standard Vth)在不導通的時候維持Standard vth
在導通的時候,Body給予一個正電壓使得Vth下降,可以讓 pull-down 速度更快
那這樣的方式有沒有誤呢
※ 編輯: bbogod 來自: 1.172.188.42 (03/22 01:02)
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如果真的觀念這樣是對的,我拿一個inv做模擬
依照我這樣說的方式加入body-bias機制,應該會得到1.速度加快 2.漏電流可能會增加
但我模擬出來的數據卻不是我說的這樣@@"所以我才懷疑是不是我觀念哪邊有誤
※ 編輯: bbogod 來自: 1.172.188.42 (03/22 01:36)
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