[問題] verilog 合成電路時的error
看02 syn.log出現很多這種error
想起問這是甚麼意思...
60: Net 'count_in[4]' or a directly connected net is driven by more than one
source, and not all drivers are three-state.
是每個if else 內的變數 重複給到值
還是?
以下是部分的code~
always@(posedge CLK,negedge RESET_n)begin
if (!RESET_n) count_in <= 0;
else if(IN_VALID==1) count_in<=count_in+1;
else if(flag_rotate==1) count_in<=count_in+1;
else if(c_state==Output)count_in<=count_in+1;
else count_in<=0;
end
還是指說我的if else語句會重疊到
就是同時執行我的code倒數 3 4 行
但是剛try 過 還是有那個error..
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※ 編輯: Goodgybank 來自: 210.64.163.158 (08/11 20:46)
※ 編輯: Goodgybank 來自: 210.64.163.158 (08/11 20:47)
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08/11 22:16, , 1F
08/11 22:16, 1F
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08/11 22:19, , 2F
08/11 22:19, 2F
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08/11 22:22, , 3F
08/11 22:22, 3F
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08/11 22:26, , 4F
08/11 22:26, 4F
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08/11 22:27, , 5F
08/11 22:27, 5F
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08/11 22:27, , 6F
08/11 22:27, 6F
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08/11 22:28, , 7F
08/11 22:28, 7F
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08/11 22:32, , 8F
08/11 22:32, 8F
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08/11 22:34, , 9F
08/11 22:34, 9F
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08/11 22:34, , 10F
08/11 22:34, 10F
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08/11 22:36, , 11F
08/11 22:36, 11F
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08/11 22:36, , 12F
08/11 22:36, 12F
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08/11 22:48, , 13F
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08/11 22:55, , 14F
08/11 22:55, 14F