[問題] verilog-a indirect branch assignments
這幾天終於大概知道verilog-a在幹嘛了
不過我實在是看不懂indirect branch assignments是什麼意思
他的manul寫範例是寫op，他原文是這樣
Consider the model for an ideal OPAMP. In this model, the output is driven to
the voltage that results in the input voltage being zero.
The constitutive equation is V(in) == 0
This can be formulated in fixed point form as
V(out) <+ V(out) + V(in);
This statement defines the output of the OPAMP to be a controlled voltage
source by assigning to V(out) and defines the input to be high impedance by only
probing the input voltage.
The desired behavior results because the description is formulated
in such a way that it reduces to V(in) = 0.
This approach does not result in the right tolerances being
applied to the equation if out and in have different disciplines.
Verilog-A HDL includes a special syntax that is appropriate in this
situation. The above branch contribution can be rewritten using an indirect branch assignment:
V(out): V(in) == 0;
which reads “find V(out) such that V(in) == 0”. It indicates that out
should be driven with a voltage source and the source voltage should be such that the given
equation is satisfied.
Any branches referenced in the equation are only probed and not
driven. In particular, V(in) acts as a voltage probe.
看不懂是什麼意思
可以麻煩大家解釋一下嗎
謝謝
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