[問題] IC compiler CTS的問題

看板Electronics作者sfox3258 (小丹尼?!)時間13年前 (2012/10/10 00:46)推噓1(1推 0噓 13→)

留言14則, 4人參與討論串1/1

想請問一下版上先進我在設計中有加入memory generator產生的register files 在DC的時候用set_ideal_network [get_clocks clk] 可以順利跑過測試但是在讀入ICC之後 remove_ideal_network [get_ports clk] 再去跑 clock_opt -fix_hold_all_clocks -no_clock_route 出來的卻是一堆 timing violation 都是register files中的clk到Q的999 舉例一個如下圖所示 Startpoint: GIF_all_ins/M1 (rising edge-triggered flip-flop clocked by clk) Endpoint: GIF_all_ins/G_top/STAGE_1/SS1/_I2_IIr_r_next1_reg[16] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Point Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (propagated) 3.00 3.00 GIF_all_ins/M1/CLKA (RF_2P_100X90) 0.00 3.00 r GIF_all_ins/M1/QA[58] (RF_2P_100X90) 999.00 1002.00 r GIF_all_ins/G_top/QA1[58] (GIF_top) 0.00 1002.00 r GIF_all_ins/G_top/STAGE_1/QA1[58] (stripe_scheduler_top) 0.00 1002.00 r GIF_all_ins/G_top/STAGE_1/SS1/QA1[58] (stripe_scheduler) 0.00 1002.00 r GIF_all_ins/G_top/STAGE_1/SS1/U407/Y (AOI222X2) 0.10 * 1002.10 f GIF_all_ins/G_top/STAGE_1/SS1/U1329/Y (CLKINVX2) 0.07 * 1002.17 r GIF_all_ins/G_top/STAGE_1/SS1/_I2_IIr_r_next1_reg[16]/D (DFFRQXL) 0.00 * 1002.17 r data arrival time 1002.17 clock clk (rise edge) 10.00 10.00 clock network delay (propagated) 2.98 12.98 clock uncertainty -0.10 12.88 GIF_all_ins/G_top/STAGE_1/SS1/_I2_IIr_r_next1_reg[16]/CK (DFFRQXL) 0.00 12.88 r library setup time -0.13 12.74 data required time 12.74 -------------------------------------------------------------------------- data required time 12.74 data arrival time -1002.17 -------------------------------------------------------------------------- slack (VIOLATED) -989.43 我是按照CIC上課的講義一步一步做的但是不知道是自己的design設定哪裡出了問題了嗎還麻煩各位解答謝謝~~ -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.112.48.126

推

onlykals

10/10 04:10, , 1^F

10/10 04:10, 1^F

→

onlykals

10/10 04:11, , 2^F

10/10 04:11, 2^F

→

onlykals

10/10 04:11, , 3^F

10/10 04:11, 3^F