[問題] verilog the fan-out number of signal "target_b_0_0" is 4
the fan-out number of signal "target_b_0_0" is 43 whereas the limitation is
10.
請問這是甚麼意思
用 nLint 跑出的錯誤
我在gate level的時候 OUT_VALID 會自動變成XX
RTL正常
我只有在這個block裡面控制而已
always @(posedge CLK) begin
if(!RESET_n)begin OUT_VALID<=0; end
else if(o1==1) begin OUT_VALID<=1; OUT<=sub_temp_com4_0_1+1; end
else if(o2==1) begin OUT<=sub_temp_com4_0_0; end
if(o3==1) begin
OUT_VALID<=0;
end
end
--
When we toss a coin , we obtain either head or tail. Now we toss a coin 5
times. There are 2^5 possible outcomes. How many of them contain no two
consecutive heads?
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.113.56.69
→
10/06 07:31, , 1F
10/06 07:31, 1F
請問我本來用 s1,s2,s3,s4..... 進入下個階段就把
s1<=0 ; s2<=1.... 這樣寫是不是不太好
後來我改成 stage 進入下個階段就把 stage <= stage+1
這樣是不是比較好
※ 編輯: bjk 來自: 140.113.56.69 (10/06 11:16)
另外再問我這樣寫法是不是會錯阿
http://codepad.org/2E7Oq9OU
我可以只宣告一次變數，讓他重複當作for的變數嗎
就像fori這樣
always @(posedge CLK)
begin
if(stage==4) begin
for(fori=0;fori<9;fori=fori+1)
for(forj=0;forj<2;forj=forj+1) begin
sub_temp3[fori][forj]<=sub_temp2[fori][forj]+sub_temp2[fori][forj+2];
end
end
end
always @(posedge CLK)
begin
if(stage==4) begin
for(fori=0;fori<9;fori=fori+1)
sub_temp4[fori][0]<=sub_temp3[fori][0]+sub_temp3[fori][1];
end
end
※ 編輯: bjk 來自: 140.113.56.69 (10/07 00:50)
推
10/07 23:41, , 2F
10/07 23:41, 2F
推
10/07 23:43, , 3F
10/07 23:43, 3F
→
10/07 23:43, , 4F
10/07 23:43, 4F
→
10/07 23:45, , 5F
10/07 23:45, 5F
→
10/07 23:45, , 6F
10/07 23:45, 6F
→
10/08 00:28, , 7F
10/08 00:28, 7F
→
10/08 14:33, , 8F
10/08 14:33, 8F
推
10/08 18:55, , 9F
10/08 18:55, 9F
→
10/08 18:55, , 10F
10/08 18:55, 10F