[問題] verilog shift reg bit數不足
input signed [3:0] IN_A,IN_B;
reg signed [7:0] temp,tempa,tempb;
寫法一
temp=(IN_A<<2)+(IN_B<<2);
寫法二
tempa=IN_A<<2;
tempb=IN_B<<2;
temp=tempa+tempb;
這兩個結果是不是會不同
--
When we toss a coin , we obtain either head or tail. Now we toss a coin 5
times. There are 2^5 possible outcomes. How many of them contain no two
consecutive heads?
--
※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.113.56.69
推
09/29 10:54, , 1F
09/29 10:54, 1F
→
09/29 15:04, , 2F
09/29 15:04, 2F
推
09/29 23:27, , 3F
09/29 23:27, 3F
→
09/29 23:28, , 4F
09/29 23:28, 4F
推
09/29 23:31, , 5F
09/29 23:31, 5F
→
09/30 15:18, , 6F
09/30 15:18, 6F
推
09/30 15:56, , 7F
09/30 15:56, 7F
→
10/01 00:51, , 8F
10/01 00:51, 8F
推
10/03 14:22, , 9F
10/03 14:22, 9F
→
10/03 14:24, , 10F
10/03 14:24, 10F
→
08/13 19:31, , 11F
08/13 19:31, 11F
→
09/17 23:25, , 12F
09/17 23:25, 12F