[問題] verilog的bug
下面的code有syntax error，可是這是錯在那呢??
code:
always @(*)begin
case(counter)
5'd0 :
if(lcd_512_1_or_0[0]==1'b1)
begin
next_PATTERN[3:0]=4'b1111;
next_PATTERN[11:8]=4'b1111;
next_PATTERN[19:16]=4'b1111;
next_PATTERN[27:24]=4'b1111;
end
else
begin
next_PATTERN[3:0]=0;
next_PATTERN[11:8]=0;
next_PATTERN[19:16]=0;
next_PATTERN[27:24]=0;
end
run的結果說下一行有Syntax error near "if".
if(lcd_512_1_or_0[1]==1'b1)
begin
next_PATTERN[35:32]=4'b1111;
next_PATTERN[43:40]=4'b1111;
next_PATTERN[51:48]=4'b1111;
next_PATTERN[59:56]=4'b1111;
end
else
begin
next_PATTERN[35:32]=0;
next_PATTERN[43:40]=0;
next_PATTERN[51:48]=0;
next_PATTERN[59:56]=0;
end
--
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