[問題] Desgin Compiler addsub合成
我想要試著去合成一個addsub電路，Verilog寫法如下：
module ADDSUB(clk,rst,A,B,Mode,Sum);
input clk;
input rst;
input [13:0]A,B;
input Mode;
output reg [13:0]Sum;
reg [13:0]AI,BI;
always@(posedge clk or posedge rst)
begin
if(rst) begin
Sum<= 0;
AI <= 0;
BI <= 0;
end
else begin
Sum<= Mode? (AI-BI):(AI+BI);
AI <= A;
BI <= B;
end
end
endmodule
事實上我希望他能夠合成出一個addsub電路，而非兩個加法器，不過卻不知道怎麼讓
DC自己和出來? 希望各位前輩能指點一下
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◆ From: 163.25.97.177
※ 編輯: chrispherd 來自: 163.25.97.177 (06/09 22:04)
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