[請益] 請問高手如何計算comparator的sensitivity?
如題
小弟該如何計算一個latch based comparator之sensitivity
(即最小的輸入差值使電路可以達到sense_amplify的功能)
此數值，可能是20mv,或是10mv等，但是要怎模擬，公式推算?????
電路圖由上而下是
One PMOS sourcing current
PMOS input differential pair
Two cross coupled inverter
size 就用W跟L表示好了
有PAPER可以示意此電路:A 1 Tb/s 3 W Inductive-Coupling Transceiver for
3D-Stacked Inter-Chip Clock and Data Link
PAGE 4上面有一個TX & RX的電路，在RX那邊就有上述電路，煩請高手幫忙解答~~
感謝!!
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