[問題] verilog的blocking和non-blocking造成的差別
如題，我想產生一個受到輸入訊號clk_chg控制的clock
使用blocking assignment能成功產生我要的波形，即下圖的 o2B
http://kr.imghost.us/6f2/sim.JPG
code如下：
module test2_blocking(clk, reset, clk_chg, clkout); //使用blocking assignment
input clk, reset, clk_chg;
output clkout;
reg clk_chg_delay, con, s;
reg [2:0] state;
wire clkout=(s)?con:clk; //在受控制的DFF(con)和clk之間做切換
always@(negedge clk) //讓clk_chg訊號delay半個cycle
clk_chg_delay=(clk_chg)?1'b1:1'b0;
always@(posedge clk)
if (reset)
begin
con=1'b0;
s=1'b0;
state=1;
end
else
if (clk_chg_delay)
begin
case(state)
1:begin
con=1'b1;
s=1'b1;
state=2;
end
2:begin
con=con;
s=1'b0;
state=3;
end
3:begin
con=1'b0;
s=1'b1;
state=1;
end
default:begin
con=1'b0;
s=1'b0;
state=1;
end
endcase
end
else
begin
con=1'b0;
s=1'b0;
state=1;
end
endmodule
但是兩個always改成 non-blocking assignment 後，
就變成圖中的o2nB，會有 glitch (紅色圓圈處)
請問原因為何？
又是否有別的方法產生我要的波形呢？ 謝謝，請多多指教^^
個人推測原因：non-blocking assignment在當下那個time step "結束" 時才更新值，
使得切換的動作慢了一點，才會有glitch；而blocking assignment在當下那個time
step "開始" 時即更新值，所以即使應該也有glitch，但因為時間太短，modelsim
忽略掉。這想法正確嗎？
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