[問題] VERILOG SHIFT REG

看板Electronics作者zx33571163 (mm)時間13年前 (2010/08/14 20:39)推噓6(6推 0噓 20→)

留言26則, 5人參與討論串1/1

always@(posedge clk or posedge reset ) begin if(!reset) begin buf1out1<=0; buf1out2<=0; buf1out3<=0; end else begin buffer[0]<=buf1in2; buffer[1]<=buf1in1; __________________________________________________________ buffer[2]<=buffer[0]; buffer[3]<=buffer[1]; buffer[4]<=buffer[2]; . . . . . . buffer[178]<=buffer[176]; buffer[179]<=buffer[177]; buffer[180]<=buffer[178]; ______________________________________________________ buf1out1<=buffer[179]; end end 中間那段怎麼寫比較快總共要寫180幾行要怎麼寫比較快? 有用過genvar for迴圈可是compile沒過= = -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 59.117.164.238 ※ 編輯: zx33571163 來自: 59.117.164.238 (08/14 20:40)

推

Acme

08/14 21:16, , 1^F

08/14 21:16, 1^F

※ 編輯: zx33571163 來自: 59.117.164.238 (08/14 21:27)

推

Acme

08/14 21:32, , 2^F

08/14 21:32, 2^F

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Acme

08/14 21:36, , 3^F