[問題] 我的verilog 除頻方法錯了??
input rst,clk;
input pause_push;
reg [23:0] driver;
wire clk1;
assign clk1=driver[23];
always @(negedge clk or negedge rst)
begin
if(!rst)
begin
driver<=24'h000000;
end
else
begin
driver<=driver+1;
end
end
always @(negedge rst or negedge clk1)
begin
.
.
.
.
以上是我的除頻方法
我燒到fpga後，我clk1 偵測不到，
請問是我的方法錯了嗎??
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