[問題] 數位邏輯電路問題
How to design a three-input NAND gate and a three-input
NOR gate.
Note:
1.Assume that the size of the PMOS and the NMOS in a
unit-size inverter are 3W/L and W/L, respectively.
2.The parasitic capacitances for the transistors are
neglected.
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5年前
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