[問題] 使用Artisan產生的memory問題

看板Electronics作者arloha (我要去澳洲玩!!!)時間16年前 (2009/09/07 16:12)推噓6(6推 0噓 15→)

留言21則, 5人參與討論串1/1

目前遇到的問題就是使用Artisan產生的sram無法得到正確的function模擬結果而我所要的function為...... ========================================================================= 由一個計數器負責產生寫入以及讀取的address 在一開始計數0~15時,會做寫入的動作,位置是取計數器count[3:0]的位元 0000000,0000001,0000010,0000011.........,0001101,0001110,0001111 接著,16~31時會做讀取的動作,位置也是取計數器count[3:0]的位元且count[4]位元是拿來判斷做讀取或寫入動作的依據最後依照上面的敘述每16個clk重複執行做寫入.讀取.寫入.讀取..... ========================================================================= 現在遇到的問題是,計數器0~15時寫入的data,在計數器16~31時應該要輸出但輸出卻是 x (don't care)的情況..... 所以想請一下有經驗的人幫忙看哪裡出錯了因為我看過datasheet使用方法應該也沒弄錯另外模擬軟體是用Verilog-XL 跟 Simvision 而在跑Verilog-XL時有出現 "sram_16x4.v", 399: Timing violation in test_tb.test.sram_16x4 $setuphold<hold>( posedge CLK &&& re_flag:1000000, posedge A[0]:1000000, 1.000 : 1000, 0.500 : 500 ); 這樣的訊息下面是我的程式碼.... PS:sram_16x4.v是由Artisan memory comiler產生,code有點長,如有需要再附上了 ========================================================================== `timescale 1ns / 1ps module test(in,rst,clk,count,out); input rst; input clk; input [3:0]in; output [6:0]count; output [3:0]out; wire [6:0]count; counter128 c128(clk,rst,count); sram_16x4 sram_16x4(out,clk,1'b0,count[4],count[3:0],in,~count[4]); // sram_16x4 ( Q,CLK,CEN,WEN, A, D, OEN ); endmodule module counter128(clk, rst,count); input clk; input rst; output [6:0] count; wire [6:0] count; reg [6:0] counter_in; assign count=counter_in; always@(posedge clk) if(rst) counter_in<=1'b0; else counter_in<=counter_in+1'b1; endmodule ============================下面是testbench=========================== `timescale 1ns / 1ps module test_tb; reg rst; reg clk; reg [3:0] in; wire [3:0] out; wire [6:0] count; test test(in,rst,clk,count,out); always #10 clk=~clk; initial begin // Initialize Inputs rst = 1; clk = 1; in = 0; #40 rst=0; #20 in=1; #20 in=3; #20 in=5; #20 in=3; #20 in=2; #20 in=7; #20 in=9; #20 in=7; #20 in=6; #20 in=4; #20 in=2; #20 in=1; #20 in=4; #20 in=7; #20 in=2; #20 in=3; ///////// #20 in=6; #20 in=8; #20 in=6; #20 in=4; #20 in=7; #20 in=9; #20 in=5; #20 in=4; #20 in=2; #20 in=6; #20 in=4; #20 in=2; #20 in=1; #20 in=4; ////////// #20 in=2; #20 in=3; #20 in=4; #20 in=4; #20 in=4; #20 in=7; #20 in=7; #20 in=3; #20 in=1; #20 in=4; #20 in=6; #20 in=3; #20 in=6; #20 in=5; #100 $finish; end initial begin $dumpfile("test.vcd"); $dumpvars(0,test); end endmodule -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.118.107.144

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pupucar

09/07 17:09, , 1^F

09/07 17:09, 1^F

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arloha

09/07 17:49, , 2^F

09/07 17:49, 2^F

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pupucar

09/07 18:34, , 3^F

09/07 18:34, 3^F