[問題] Circuit optimization by Hspice

看板Electronics作者 (唸個書吧~哞!)時間15年前 (2009/07/05 23:13), 編輯推噓2(2推 0噓 7→)
留言9則, 1人參與, 最新討論串1/1
Hello~everyone Here I have some question about circuit optimization by Hspice Could I get these best W/L of each transistor by for loop method? There is no answer through Google and I came up with some idea to solve it. The idea is that I write some statements like that below: Step 1: .... .atler .param w1=200, l1=5, w2=100, l2=3.6 .......brabra ...Vout is saved to file .end If I want to try many w/l(ex:w=200 to 300, step=10,keep the same l1), then changing some values of some transistors and repeat statements Step 2: .... load txt file to Excel and use macros to get the best W/Ls to meet output. .... I think the work mentioned above is okay(I haven't tried it yet).But it's exhausting. Do u anyone have any better idea? Thank you all! -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 122.123.134.39 ※ 編輯: kyokanasaki 來自: 122.123.134.39 (07/05 23:20) ※ 編輯: kyokanasaki 來自: 122.123.128.189 (07/06 19:49)
推
07/09 23:46, , 1F
usually there're dozen of transistors in a analog ckt
07/09 23:46, 1F
→
07/09 23:50, , 2F
tweak one of them could not optimize overall performance
07/09 23:50, 2F
→
07/09 23:55, , 3F
I think you can consult some traditional design flow first
07/09 23:55, 3F
→
07/09 23:58, , 4F
once you are familiar with it, you would know which
07/09 23:58, 4F
→
07/10 00:00, , 5F
transistors should be tweaked larger or small, you
07/10 00:00, 5F
推
07/10 00:09, , 6F
can do this by iteration. you should know what parameter
07/10 00:09, 6F
→
07/10 00:12, , 7F
you want to be optimum(power, swing, linearity...)
07/10 00:12, 7F
→
07/10 00:16, , 8F
different parameters result in differdnt difficulty on
07/10 00:16, 8F
→
07/10 00:17, , 9F
optimum. there are no one rule can optimize all of them
07/10 00:17, 9F
‣ 更多 kyokanasaki 的文章
文章代碼(AID): #1AKCB_5R (Electronics)