[問題] vhdl做一個暫存器
小弟現在想用VHDL做一個暫存器
大致的結構如下
INPUT -> G -> F -> E -> D -> C -> B -> A -> OUT
但一次要讀 7 個暫存器的資料
假如我今天一列資料串是這樣輸入111001011100101110010.....
讀出來的資料要為 DATAOUT是從A開始讀起 大概如下
1s 1110010
2s 1100101
3s 1001011......依此類推
我的程式如下
entity register_pn is
port(
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
data_in : IN STD_LOGIC;
reg_data_out : OUT STD_LOGIC_VECTOR (6 downto 0)
);
end register_pn;
architecture Behavioral of register_pn is
begin
process (clk,reset)
variable reg_a,reg_b,reg_c,reg_d,reg_e,reg_f,reg_g : STD_LOGIC;
variable reg_a1 : STD_LOGIC;
begin
if (reset = '0') then
reg_a:='0';
reg_b:='0';
reg_c:='0';
reg_d:='0';
reg_e:='0';
reg_f:='0';
reg_g:='0';
reg_a1:='0';
reg_data_out <= "0000000";
elsif (reset = '1' and clk'event and clk = '0') then
reg_a:=reg_b;
reg_b:=reg_c;
reg_c:=reg_d;
reg_d:=reg_e;
reg_f:=reg_f;
reg_f:=reg_g;
reg_g:=reg_a1;
data_in<=reg_a1;
reg_data_out(0) <= reg_a;
reg_data_out(1) <= reg_b;
reg_data_out(2) <= reg_c;
reg_data_out(3) <= reg_d;
reg_data_out(4) <= reg_e;
reg_data_out(5) <= reg_f;
reg_data_out(6) <= reg_g;
end if;
end process;
end Behavioral;
現在遇到的困難是 出現一個ERROR
Object data_in of mode IN can not be updated
應該是說 IN 這邊沒辦法丟新的資料進來
不太懂說為什麼無法丟 我只是把下一個資料丟到G而已 然後做移位
請版上的高手們幫幫忙吧 謝謝... 感恩
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