[問題] 如何在沒有reset下去計數clock
如果只有一個input，且是一個clock，而要輸出reset跟一些其他訊號，目前卡在如何去
計數clock，我的寫法如下:
input clock;
reg state;
reg [8:0] count;
always @(posedge clock)
begin
state <= 1'b0;
end
always @(posedge clock )
begin
if (~state)
count <= 8'd0; // initial count=0
end
always @(posedge clock)
if (~count)
count <= count + 1;
modelsim模擬結果，這樣是可以計數clock，可是要合成電路會有錯誤，"Only one
always block may assign a given variable count[8:0]" 現在想不通如何把下面兩個
always合成一個always呢? 謝謝了!
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