[問題] VLSI設計

看板Electronics作者s552400 (<(_ _)>請多指教)時間18年前 (2008/01/12 00:05)推噓3(3推 0噓 4→)

留言7則, 6人參與討論串1/1

Please design a divided-by-8 frequency divider with three cascaded DFFs as shown below. The clock frequency is 1MHz. Please show: 1.Schematic of the DFF. 2.Waveforms to verify the function of DFF. 3.Simulation waveforms for CLK, Q1, Q2 and Q3. 4.Layout and post-simulation results. __________________ ___________________ ___________________ | ___________ | | ___________ | | ___________ | | | | | | | | | | | | | |__| D Q | | |___| D Q | | |___| D Q | | | Q1 | | | Q2 | | | Q3 | | | _ | | | _ | | | _ | | CLK--> |> Q |___|------|> Q |___|------|> Q |___| |___________| |___________| |___________| 這是期末project,但h-spice程式部份不知如何著手. 想求點提示謝謝 -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 163.25.118.141

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jingwoei

01/12 00:24, , 1^F

01/12 00:24, 1^F

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oorr

01/12 13:56, , 2^F

01/12 13:56, 2^F

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ckl12345

01/13 11:45, , 3^F

01/13 11:45, 3^F