[問題]SATA spec.-SSC jitter measurement (CDR corner frequency)
SATA spec.-SSC jitter measurement (CDR corner frequency)
In SATA specification, jitter is defined as the difference in time between a
data transition and the associated Reference Clock event for Gen1x, Gen2i and
Gen2x. SATA assumes a BER target of less than 10-12. The Reference Clock is
extracted from a serial data stream using either a PLL (hardware) or a clock
recovery algorithm (software).
Reference Clock PLL are defined as type 2 PLL with a -3 dB corner frequency
fc3db = fBAUD / N. Several corner frequencies are provided in the jitter
budget fc3db = fBAUD / 10 (Gen2i, Gen2m), fc3db = fBAUD / 500 (Gen2i, Gen2m),
fc3db = fBAUD / 1667 (Gen1x, Gen2x).For Gen2i and Gen2m, transmitters and
receivers shall meet fBAUD / 10 and fBAUD / 500 specifications.
How to calculate the technical origin of the number 1667 or 500? Is there some
mathematical or technical explanation for it?
I have read the Annex C in MJSQ (Method for Jitter and Signal Quality)
document, but I can't get the answer .
Thank you!!
因為之前在國外的論壇發問 但沒得到答案 所以就直接複製過來用爛英文PO版問了
想問 fc3db = fBAUD / 500的 1/500或 1/1667 這數字怎麼來的？
只知道是依 jitter budget 推出來的 但比較詳細的數學就不知道怎麼導
不知道有沒有人清楚 謝謝！
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※ 編輯: alomer 來自: 140.113.252.215 (10/28 18:30)
※ alomer:轉錄至看板 comm_and_RF 10/28 18:32