[問題] layout

看板Electronics作者BruceBowen12 (just defense)時間18年前 (2007/08/03 12:18)推噓9(9推 0噓 6→)

留言15則, 6人參與討論串1/1

各位前輩好在做drc時出現以下的這個問題 T.3P { @ N-well pickup OD to PMOS space > 30um NWELi_US = SIZE NWELi BY - 0.085 // 0.12/1.415 = 0.085 // 30/1.415 = 21.201, (0.6 + 2 * 0.085)/1.415 = 0.544 NTAP_OS = SIZE NTAP BY 21.201 INSIDE OF NWELi_US STEP 0.544 TRUNCATE 0.544 PASD_FAR = PASD NOT NTAP_OS PASD_FAR_FILTER = SIZE PASD_FAR BY 30 NTAP_NEAR = NTAP INTERACT PASD_FAR_FILTER // doing an more accurate sizing NTAP_NEAR_OS = SIZE NTAP_NEAR BY 0.10 NTAP_90_CORNER = INT NTAP_NEAR_OS < 0.06 ABUT==90 INTERSECTING ONLY REGION NTAP_OCT = NTAP_NEAR_OS NOT NTAP_90_CORNER NTAP_135_CORNER = INT NTAP_OCT < 0.04 ABUT>134<136 INTERSECTING ONLY REGION NTAP_HEX = NTAP_OCT NOT NTAP_135_CORNER // 30-0.10 = 29.9 NTAP_HEX_OS = SIZE NTAP_HEX BY 29.9 INSIDE OF NWELi_US STEP 0.544 TRUNCATE 0.544 PASD_FAR NOT NTAP_HEX_OS } 導致在做lvs時找不到pmos body的電壓找了半天不知道是那裡出錯了我是用laker去畫的兩個pmos的共用端我是用疊起來的外面在畫nwell pmos是直接拿內建的希望高手大大能幫忙一下小弟>"< -- ※ 發信站: 批踢踢實業坊(ptt.cc) ◆ From: 140.123.112.130

推

BuBuChen

08/03 13:08, , 1^F

08/03 13:08, 1^F

推

BruceBowen12

08/03 13:53, , 2^F

08/03 13:53, 2^F

推

points333

08/03 21:48, , 3^F

08/03 21:48, 3^F