[問題] `timescale in verilog
剛剛compile的時候出現了下面的error訊息
Compiling source file "fulladder.v"
Compiling source file "fulladder_t.v"
Error! Module (full_adder) has a `timescale directive
but previous modules do not [Verilog-MODTDN]
"fulladder_t.v", 1: module full_adder(sum, c_out
, a, b, c_in);
1 error
我把`timescale移來移去都還是會出錯
我想做的是在full-adder中1ns/10ps
testbench中10ns/10ns
請問要怎麼做呢? 感謝
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