討論串i386 version of cpu_sfence()
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Hmm. Well, for it not to be globally ordered processor 1 would. have to be able to have visibility on a second write before it. has visibility on the
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On Sat, Jan 29, 2011 at 2:54 AM, Matthew Dillon. <dillon@apollo.backplane.com> wrote:. >. > :Hi all,. > :. > :i386 version of cpu_sfence(), it is just
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cpu_sfence() is basically a NOP, because x86 cpus already order. writes for global visibility. The volatile ..."memory" macro is. roughly equivalent t
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Hi all,. i386 version of cpu_sfence(), it is just asm volatile ("" :::"memory"). According to the instruction set, sfence should also ensures that the
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